Improvements in integrated circuit technology have produced smaller devices with higher performance and reduced power consumption. These improvements may be employed in the fabrication of integrated circuits such as integrated circuit memories. One such memory comprises a one time programmable memories (OTPs). When designing or fabricating a one time programmable memory (OTP), the supply voltages that are used to power the OTP may be large because of internal design requirements. Such internal design requirements may be related to the voltage level requirements of the individual components that are used to implement the OTP. These voltage levels may be related to proper biasing of the electronic components in the OTP. When an OTP is implemented using NMOS (n channel MOSFET) logic, proper forward biasing of an n channel MOSFET may result in a voltage drop, VT, across the gate to the drain of such a transistor, for example. Unfortunately, such voltage drops may relate to increases in power consumption when operating a one time programmable memory (OTP).
The limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.